The exemplary embodiments of this invention relate generally to semiconductor devices and techniques for the fabrication thereof and, more specifically, to the fabrication of complementary metal oxide semiconductor (CMOS) devices processed with III-V materials.
A complementary metal oxide semiconductor device (CMOS) uses pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) arranged on silicon or silicon-on-insulator (SOI) substrates. A MOSFET, which is used for amplifying or switching electronic signals for logic functions, has source and drain regions connected by a channel. The source region is a terminal through which current in the form of majority charge carriers enters the channel, and the drain region is a terminal through which current in the form of majority charge carriers leaves the channel. In a p-type MOSFET (hereinafter “PFET”), the majority charge carriers are holes that flow through the channel, and in an n-type MOSFET (hereinafter “NFET”), the majority charge carriers are electrons that flow through the channel. The channel may be defined by an element such as one or more fins, one or more nanowires, or one or more sheets, such fins, nanowires, or sheets including silicon. One or more gates are positioned over or around the channel to control the flow of current between the source and drain regions.
The channels may be fabricated of, for example, germanium or III-V materials. In forming channels, III-V materials have previously been grown on mandrels (or after the formation of any dummy gates but before the formation of replacement metal gates (RMG)). However, processing of PFETs generally involves high temperatures, which may be unsuitable with regard to III-V materials. In particular, PFET processing typically involves a high-k reliability anneal, and since the temperatures at which such an anneal is carried out may be incompatible with any III-V materials utilized, at least some PFET processes have avoided the anneal. Furthermore, prior processes have utilized two III-V sidewall growths that result in colliding growth fronts, which has generally resulted in lattice mismatch along the interface of the two growths, thereby contributing to decreased PFET performance.